module UART(tx_data,trmt, tx_done, clk, rst_n, TX, RX, rx_data, rdy, clr_rdy);

input trmt, clk, rst_n, clr_rdy, RX;
output tx_done, rdy, TX;

input [7:0]tx_data;
output [7:0]rx_data;

//These are instatiating the recieving block and transmitting block
//with the input and output values.
UART_tx TRANS(clk, rst_n, TX, tx_data, trmt, tx_done);
UART_rx REC(rx_data, rdy, clr_rdy, clk, rst_n, RX);





endmodule
